
J. (Ram) Ramanujam
| 102 Electrical Engineering Building | Office: | +1 (225) 578-5628 |
| Department of Electrical and Computer Engineering | Fax: | +1 (225) 578-5200 |
| and Center for Computation and Technology (302 Johnston Hall) | Dept.: | +1 (225) 578-5241 |
| Louisiana State University, Baton Rouge, LA 70803-5901, USA | E-mail: | j x r {@} ece.lsu.edu |
| Research |
| Research Interests |
Compiler optimizations for high performance computers: GPUs, multicore, accelerators. Embedded systems: compilers, design, processors Parallel computing: architecture, algorithms, software Computer architecture Compilers, operating systems and architectures for low power Hardware synthesis and optimization: behavioral-level, logic-level
| Current and Recent Research Grants |
« NSF Strategic Technologies for Cyberinfrastructure (OCI STCI) grant: An Environment for Portable High Productivity High Performance Computing on GPUs/Accelerators, 2009-12 « NSF Computing Processes and Artifacts (CISE CCF) Compilers grant: An Effective Automatic Parallelization Framework for Multi-Core Architectures, 2008-11
« NSF Computing Processes and Artifacts (CISE CCF) Compilers grant: Search-Based Model-Driven Framework for Compiler Optimizations, 2006-10 « NSF Computer Systems Research (CISE CSR) grant: CSR-AES: An Integrated Framework for Compile-time/Run-time Support for Multi-Scale Applications on High-End Systems, 2005-09 « NSF Nanoscale Exploratory Research grant: NER: Integration of Ab-Initio Computation with Large Scale Molecular Dynamics Simulation for Nanomaterials Research, 2005-07 « NSF Information Technology Research (ITR) grant: Synthesis of High Performance Algorithms for Electronic Structure Calculations, 2001-07 « NSF DDDAS (CISE) grant: DynaCode: A General DDDAS Framework with Coast and Environment Modeling Applications, 2006-07 « Environmental Protection Agency (EPA) grant: Modeling Impacts of Climate Change on Wetland Ecosystems, 2002-05 « NSF (CISE) grant: Research and Training in Advanced Compiler Optimizations, 2001-05 « NSF (CISE) grant: Program and Storage Transformations for Improving Memory Performance, 2000-04
| Software |
PLUTO - An automatic parallelizer and locality optimizer for multicores Download PLUTO
PrimeTile -- A parametric multi-level tiler for imperfect loop nests PrimeTile website Download PrimeTile
| Publications |
h-index: 32. g-index: 50.
Recent Publications (most in pdf)
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Full List of Publications (some pdf included)
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Publications (from Google Scholar)
Recent Articles (from Google Scholar)
Publications (from the new DBLP)Selected Recent Publications
L.-N. Pouchet, U. Bondhugula, C. Bastoul, A. Cohen, J. Ramanujam, P. Sadayappan and N. Vasilache, "Loop Transformations: Convexity, Pruning and Optimization," in Proc. Symposium on Principles of Programming Languages (POPL 11), Austin, TX, January 2011.
H. Salamy and J. Ramanujam, "Storage Optimization through Offset Assignment with Variable Coalescing," in ACM Transactions on Embedded Computing Systems, 2010.
L.-N. Pouchet, U. Bondhugula, C. Bastoul, A. Cohen, J. Ramanujam and P. Sadayappan, "Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework," in Proc. ACM/IEEE Conference on High Performance Computing SC10, New Orleans, LA, November 2010.
M. Baskaran, A. Hartono, S. Tavarageri, T. Henretty, J. Ramanujam, and P. Sadayappan, "Parameterized Tiling Revisited," International Symposium on Code Generation and Optimization (CGO), Toronto, Canada, April 2010.
M. Baskaran, J. Ramanujam, and P. Sadayappan, "Automatic C-to-CUDA Code Generation for Affine Programs ," International Conference on Compiler Construction (CC), Paphos, Cyprus, March 2010.
- Q. Lu, C. Alias, U. Bondhugula, T. Henretty, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan, Y. Chen, H. Lin, T. Ngai, "Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors," Proc. Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), Raleigh, NC, September 2009.
- A. Hartono, M. Baskaran, C. Bastoul, A. Cohen, S. Krishnamoorthy, B. Norris, J. Ramanujam, and P. Sadayappan, "Parametric multi-level tiling of imperfectly nested loops,'' ACM International Conference on Supercomputing (ICS), New York, NY, June 2009.
- M. Baskaran, N. Vydhyanathan, U. Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan, "Compiler-Assisted Dynamic Scheduling for Effective Parallelization of Loop Nests on Multicore Processors," in Proc. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009), Raleigh, NC, February 2009.
- A. Hartono, Q. Lu, T. Henretty, S. Krishnamoorthy, H. Zhang, G. Baumgartner, D. E. Bernholdt, M. Nooijen, R. Pitzer, J. Ramanujam, and P. Sadayappan, "Performance Optimization of Tensor Contraction Expressions for Many-Body Methods in Quantum Chemistry," The Journal of Physical Chemistry A, Vol. 113 (45), pp. 12715-12723, 2009.
- Hassan Salamy and J. Ramanujam, "A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip," in Proc. 4th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC 2009), Paphos, Cyprus, January 2009.
- M. Baskaran, U. Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan, "A compiler framework for optimization of affine loop nests for GPGPUs," ACM International Conference on Supercomputing (ICS), June 2008.
- U. Bondhugula, A. Hartono, J. Ramanujam, and P. Sadayappan, "PLUTO: A Practical and Fully Automatic Polyhedral Program Optimization System," Proc. ACM SIGPLAN 2008 Conference on Programming Language Design and Implementation (PLDI 08), Tucson, AZ, June 2008.
- U. Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan, "Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model," in Proc. CC 2008 - International Conference on Compiler Construction, March-April 2008.
- M. Baskaran, U. Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev and P. Sadayappan, "Automatic Data Movement and Computation Mapping for Multi-level Parallel Architectures with Explicitly Managed Memories," in Proc. 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, (PPoPP 2008), Salt Lake City, UT, February 2008.
- S. Krishnamoorthy, M. Baskaran, U. Bondhugula, J. Ramanujam, A. Rountev and P. Sadayappan, "Effective Automatic Parallelization of Stencil Computations," in Proc. ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation (PLDI 07), San Diego, CA, June 2007.
- U. Bondhugula, J. Ramanujam, and P. Sadayappan, "Automatic Mapping of Nested Loops to FPGAs," in Proc. ACM SIGPLAN 2007 Symposium on Principles and Practice of Parallel Programming (PPoPP 07), San Jose, CA, March 2007.
- J. Ramanujam, J. Hong, M. Kandemir, A. Narayan, and A. Agarwal, "Estimating and Reducing the Memory Requirements of Signal Processing Codes for Embedded Processor Systems," IEEE Transactions on Signal Processing, vol. 54, no. 1, pp. 286--294, January 2006.
- G. Baumgartner, A. Auer, D. Bernholdt, A. Bibireata, V. Choppella, D. Cociorva, X. Gao, R. Harrison, S. Hirata, S. Krishnamoorthy, S. Krishnan, C. Lam, Q. Lu, M. Nooijen, R. Pitzer, J. Ramanujam, P. Sadayappan, and A. Sibiryakov, "Synthesis of High-Performance Parallel Programs for a Class of ab initio Quantum Chemistry Models," Proceedings of the IEEE, vol. 93, no. 2, pp. 276-292, February 2005.
- X. Gao, S. Sahoo, Q. Lu, G. Baumgartner, C. Lam, J. Ramanujam, and P. Sadayappan, "Performance Modeling and Optimization of Parallel Out-of-Core Tensor Contractions," in Proc. ACM SIGPLAN 2005 Symposium on Principles and Practice of Parallel Programming, Chicago, IL, June 2005.
- S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C. Lam, J. Ramanujam, P. Sadayappan, and V. Choppella, "Efficient Synthesis of Out-of-Core Algorithms Using a Nonlinear Optimization Solver," Journal of Parallel and Distributed Computing, vol. 66, no. 5, pp. 659-673, May 2006. An ealier version appears as:
S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C.-C. Lam, J. Ramanujam, and P. Sadayappan, "Efficient Synthesis of Out-of-core Algorithms Using a Nonlinear Optimization Solver," In Proceedings of the 18th International Parallel and Distributed Processing Symposium (2004 IPDPS Conference), April 2004. (Best Paper Award)
- S. Krishnan, S. Krishnamoorthy, G. Baumgartner, D. Cociorva, C.-C. Lam, P. Sadayappan, J. Ramanujam, D. E. Bernholdt, and V. Choppella, "Data Locality Optimization for Synthesis of Efficient Out-of-Core Algorithms," In Proceedings of the International Conference on High-Performance Computing (HiPC '03), December 2003, (Best Paper Award)
- D. Cociorva, G. Baumgartner, C. Lam, P. Sadayappan, J. Ramanujam, M. Nooijen, D.E. Bernholdt, R. Harrison, "Space-Time Trade-Off Optimization for a Class of Electronic Structure Calculations," In Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design and Implementation (PLDI '02), June 2002, pp. 177-186.
| Research Links |
NSF Young Investigator Award, 1994.
Ritter Distinguished Professor of Electrical Engineering, 2005-present.
Distinguished Visitor, IEEE Computer Society, 2001-2003.
Best Paper Award (Applications Track) for "Efficient Synthesis of Out-of-core Algorithms Using a Nonlinear Optimization Solver," (authors: S. Krishnan, S. Krishnamoorthy, G. Baumgartner, C. Lam, J. Ramanujam, and P. Sadayappan) at the 18th International Parallel and Distributed Processing Symposium (2004 IPDPS Conference), Santa Fe, April 2004.
Best Paper Award (Systems) for "Data Locality Optimization for Synthesis of Efficient Out-of-Core Algorithms," (authors: S. Krishnan, S. Krishnamoorthy, G. Baumgartner, D. Cociorva, C. Lam, P. Sadayappan, J. Ramanujam, D. Bernholdt, and V. Choppella) at the International Conference on High Performance Computing (HiPC 03), December 2003.Beyond the PC - Application specific systems: design and implementation, Ecole normale supérieure de Lyon, Lyon, France, February 15-19, 2010
ACACES 2009: Fifth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems, Terrassa (near Barcelona), Spain, July 12-18, 2009.
Call for Papers:
- Upcoming parallelism/HPC/compiler conference deadlines (maintained locally at LSU)
- Links to Conferences, Journals, ... (maintained by Chandra Krintz)
- Related Conferences for ParaMount Groups (maintained by ParaMount Group - Rudolf Eigenmann)
- Conferences and Workshops of Interest (maintained by Jaewook Shin)
- Future deadlines for events (old name = EDA/CAD list) (maintained by Dirk Stroobandt)
- Upcoming and Recent FPGA/VLSI/CAD Conferences (maintained by Steve Wilton)
- Microelectronic Systems News Calendar (maintained by Don Bouldin)
| Teaching |
| Fall 2010 |
Fall 2010: EE 7785: Compiler Optimizations
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| Recent Courses |
Spring 2010: EE 4702: High-Level Synthesis Fall 2009: EE 7000: Software Optimizations for Multicore Spring 2009: EE 4760: Introduction to Compiler Optimizations Fall 2008: EE 7785: Compiler Optimizations Spring 2008: EE 4702: High-Level Synthesis & Embedded Systems Fall 2007: EE 7785: Compiler Optimizations Spring 2007: EE 4760: Introduction to Compiler Optimizations Fall 2006: EE 7000: Embedded Systems Spring 2006: EE 7000: High-Level Synthesis Fall 2005: EE 7785: Compiler Optimizations Spring 2005: EE 4760: Introduction to Compiler Optimizations Fall 2004: EE 7700: Architectures & Algorithms for Digital Signal Processing (DSP) Spring 2004: EE 7700: Energy Aware Computing Systems Fall 2003: EE 4702: High Level Synthesis Fall 2003: EE 7700-1: Compiler Optimizations
Spring 2003: EE 7700: Embedded Systems
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Phone List ECE Department (at LSU)
College of Engineering, Louisiana State University (LSU)
Course Offerings: Louisiana State University (LSU)